SI4021-A1-FT【PDF 12/34 页】IC TX FSK 915MHZ 5.4V 16-TSSOP

Si4021

CONTROL INTERFACE

Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK

whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer

multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first

(e.g. bit 15 for a 16-bit command). Bits having no influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default

values in all control and command registers.

The status information or received data can be read serially over the IRQ pin. Bits are shifted out upon the falling edge of CLK signal

Timing Specification

Symbol

Parameter

Minimum value [ns]

Clock high time

Clock low time

Select setup time (nSEL falling edge to SCK rising edge)

Select hold time (SCK falling edge to nSEL rising edge)

SHI

Select high time

Data setup time (SDI transition to SCK rising edge)

Data hold time (SCK rising edge to SDI transition)

Data delay time

Push-button input low time

Timing Diagram

SCK

SDI

nIRQ

nSEL

BIT15

BIT14

BIT13

POR

BIT8

BIT7

WK-UP

nIRQ

BIT1

BIT0

SHI

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